Pinnacle 1.2

Pinnacle 1.2 presents the first direct circuit-level simulations demonstrating logical error rates low enough for RSA-2048 factoring, enabled by Crevasse, our new QLDPC decoder. Combining this validation with circuit optimisations, we find that factoring can be performed at a spacetime cost an order of magnitude lower than estimated in Pinnacle 1.0, without changing the underlying architecture.

Crevasse has a mean decoding time of four microseconds per round of error correction. We use it to process trillions of simulated error correction instances, directly demonstrating a logical error rate below one error per trillion logical qubit-cycles, without relying on extrapolation or indirect statistical estimation.

We also compile a complete, verified modular exponentiation circuit into Pinnacle’s fault-tolerant instruction set and directly count the resulting operations. We use these counts and the simulated logical error rates to establish that smaller code distances suffice for factoring and to rigorously calculate the resulting spacetime cost.

Figure 1 shows the results of simulations of Pinnacle’s memory and processing blocks.

Memory experiments correspond to the idle operation of Pinnacle’s memory blocks, accounting for both X and Z type logical errors. Because memory is much larger than other modules, idle operation accounts for the majority of logical cycles for RSA-2048 factoring on Pinnacle using standard circuits. It therefore requires the lowest logical error rate of the architecture, requiring a rate per logical qubit-cycle of less than 10⁻¹². From one trillion samples in each case, we observed:

• Three logical errors on Pinnacle’s d = 16 (i.e., [[254,14,16]]) code at a physical error rate of p = 10⁻³. This implies a logical error rate of 2 × 10⁻¹³ per logical qubit-cycle, with a 95% confidence interval of [8 × 10⁻¹⁴, 7 × 10⁻¹³].

• No logical errors on Pinnacle’s d = 10 (i.e., [[126,12,10]]) code at a physical error rate of p = 10⁻⁴. This implies a logical error rate of no more than 3 × 10⁻¹³ per logical qubit-cycle, based on a one-sided 95% confidence interval.

These results validate that sufficiently low logical error rates for RSA-2048 factoring are achievable, even with smaller codes than those assumed in Pinnacle 1.0, which used the [[254,12,10]] and [[510,16,24]] codes at p = 10⁻⁴ and p = 10⁻³, respectively. Substituting the smaller codes reduces space overhead by approximately 40% and time overhead by approximately 30% relative to the estimates of Pinnacle 1.0.

Figure 1 also shows simulation results for Pinnacle’s processing blocks. We simulate random sequences of Pauli product measurements on both a single processing block and two bridged processing blocks. This models the operation of a processing unit, where the non-deterministic Clifford frame arising from Pauli-based computation effectively randomises measurement bases in large computations. Across these simulations, processing block logical error rates remain comparable to those of memory, with their contribution to overall logical errors remaining small relative to the much larger memory. We also simulated the effect of increasing the number of processing blocks in a processing unit, using the [[30,8,4]] and [[62,10,6]] codes as case studies. As shown in Figure 2, increasing the number of blocks has minimal effect on the logical error rate.

We also performed simulations to validate that Pinnacle’s magic engines output magic states of sufficient fidelity for RSA-2048 factoring. We simulated the injection of fifteen states from ancillary surface codes into Pinnacle code blocks, as required for magic state distillation. This was done in two batches of parallel injection, with up to eight states in each batch, using r = (d + 2)/3 rounds of syndrome extraction per batch. This corresponds to a throughput high enough to allow distillation to complete in one logical cycle of d + 2 rounds (accounting for error-detection measurements at the end of the distillation circuit that also require r rounds). Post-selection is performed on each of these injections using a forced gap strategy; rejection of any injection in this post-selection is factored into the overall reject rate of the magic engine. From these simulations, we find an error rate per injection of (1.3 ± 0.3) × 10⁻⁶ for the d = 10 code at a physical error rate of p = 10⁻⁴, and an error rate of (1.9 ± 0.4) × 10⁻⁵ for the d = 16 code at a physical error rate of p = 10⁻³. These results validate that injection has minimal effect on the error rate when injecting states with an input error rate of p_in = 10⁻⁴, which ensures that distillation will produce output states with a logical failure rate close to p_out ≈ 35p_in³ = 3.5 × 10⁻¹¹, sufficient for RSA-2048 factoring.

We validate the modular exponentiation circuits for factoring in Pinnacle 1.0 by verifying the correctness on a large sample of random classical inputs, similarly to the method used by Google to verify elliptic curve point addition circuits. We then compile the validated circuit using exact circuit transformations into an equivalent circuit containing only instructions implementable on Pinnacle 1, such as Pauli product measurements. We validate the compiled circuit against models of the relevant Pinnacle 1 instantiations by streaming the complete sequence of instructions required for factoring and verifying that each satisfies the architecture’s constraints. We compute the physical qubit count by summing over the qubit counts of all modules in the model. We calculate the runtime per factoring shot from the execution times of the compiled instructions, accounting for those performed in parallel. We then multiply this by the expected number of shots, accounting for failure probability per shot implied by simulated logical error rates, to give the total expected runtime. As shown in Figure 3, the resources required for factoring using the circuits of Pinnacle 1.0 agree closely with our original estimates.

We used the same software to develop and validate more efficient logical circuits for factoring. We compiled these circuits to Pinnacle 1 using codes of distances d = 10 and d = 16 for physical error rates of p = 10⁻⁴ and p = 10⁻³ respectively, in accordance with the performance validation results. The results of these circuits, compared with the circuits from Pinnacle 1.0, are shown in Figure 3. With these improved circuits, we find the updated resource estimates shown in Table 1. We also applied the improved circuits and reduced code distance to Frozen Pinnacle, and obtained a reduced estimate of 99 thousand physical qubits with an expected runtime of 5.0 days for fixed-connectivity superconducting systems.

Pinnacle 1.2 is a major advance in the validation of Pinnacle, establishing that RSA-2048 factoring can be performed on Pinnacle 1 with substantially lower resource costs than we previously estimated. These reductions come entirely from optimising the existing Pinnacle 1 architecture and the circuits it runs, informed by our validation results.

Planned architectural improvements, for example through the incorporation of lifted surgery as presented in Pinnacle 1.1, are not yet reflected in these estimates and will further reduce resource costs.